PC87591L datasheet(358/437 Pages) NSC

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Host-Controlled Modules and Host Interface (Continued)

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Revision 1.07

Signal Parameters

The signal levels should conform to the voltage level requirements for 32KCLKIN/32KX1, stated in Section 7 on page 372.

The signal should have a duty cycle of approximately 50%. To oscillate during power-down, it should be sourced from a

battery-backed source. This guarantees that the RTC delivers updated time/calendar information.

6.2.5

Timing Generation

The timing generation function divides the 32.768 KHz clock by 215 to derive a 1 Hz signal, which serves as the input for the

seconds counter. This is performed by a divider chain composed of 15 divide-by-two latches, as shown in Figure 115.

Figure 115. Divider Chain Control

Bits 6-4 (DV2-0) of CRA register control the following functions:

●

Normal operation of the divider chain (counting)

●

Divider chain reset to 0

●

Oscillator activity when only VBAT power is present (backup state).

The divider chain can be activated by setting normal operational mode (bits 6-4 of CRA = 0102). The first update occurs

500 ms after divider chain activation.

Bits 3-0 of CRA register select one the of 15 taps from the divider chain to be used as a periodic interrupt. The periodic flag

becomes active after half of the programed period has elapsed, following divider chain activation.

See “RTC Control Register A (CRA)” on page 367 for more details.

6.2.6

Timekeeping

Data Format

Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24-hour

format, as determined by bit 1 of this register.

Note: When changing the above formats, re-initialize all the time registers.

Daylight Saving

Daylight saving time exceptions are handled automatically, as described in the RTC Control Register B (CRB) in

Section 6.2.15 on page 363.

Leap Years

Leap year exceptions are handled automatically by the internal calendar function. Every four years, February is extended to

29 days. Year 2000 is a leap year.

32.768 KHz

1Hz

Divider Chain

DV2 DV1 DV0

CRA Register

Oscillator

Enable

32KX1 /

32KX2

To other

Reset

modules

32KCLKIN

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