PC87591L datasheet(362/437 Pages) NSC

362 / 437 page

Host-Controlled Modules and Host Interface (Continued)

www.national.com

362

Revision 1.07

6.2.12 Oscillator Activity

The RTC oscillator is active if:

●

VCC power supply is higher than VCCON, independent of the battery voltage, VBAT.

●

VBAT power supply is higher than VBATMIN whether or not VCC is present.

The RTC oscillator is disabled in the following cases:

●

During power-down (VBAT only), if the battery voltage drops below VBATMIN, the PC87591x may enter Battery Fail

state. In this case, the oscillator may stop oscillating and memory contents may be corrupted or lost.

●

Software wrote 00X to DV2-0 bits of CRA register and VCC is removed. This disables the oscillator and decreases

the power consumption from the battery connected to the VBAT pin. When disabling the oscillator, the CMOS RAM is

not affected as long as the battery is present at a correct voltage level.

If the RTC oscillator becomes inactive, the following features are dysfunctional/disabled:

●

Timekeeping

●

Periodic interrupt

●

Alarm

6.2.13 Interrupt Handling

The RTC has a single Interrupt Request line, which handles the following three interrupt conditions:

●

Periodic interrupt

●

Alarm interrupt

●

Update end interrupt

The interrupts are generated if the respective enable bits in CRB register are set prior to an interrupt event occurrence.

Reading the CRC register clears all interrupt flags. Therefore, when multiple interrupts are enabled, the interrupt service

routine should first read and store the CRC register and then deal with all pending interrupts by referring to this stored status.

If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost.

Figure 121 illustrates the interrupt timing in the RTC.

Figure 121. Interrupt/Status Timing

Flags (and IRQ) are reset at the conclusion of CRC read

or by reset.

Update In Progress bit high before

update occurs = 244

µs

Periodic interrupt to update

Period (periodic int) / 2 + 244

µs

C =

Update to Alarm Interrupt = 30.5

µs

Period is programed by RS3-0 of CRA

Bit 7

Bit 4

Bit 6

Bit 5

of CRA

of CRC

P/2

244

µs

30.5

µs

PC87591L 데이터시트(PDF) 362 Page - National Semiconductor (TI)

PC87591L 데이터시트(HTML) 362 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL