GXM datasheet(103/244 Pages) NSC

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Integrated Functions (Continued)

4.3

MEMORY CONTROLLER

The memory controller operates with the Processor Inter-

face (X-Bus), Display Controller Interface, Graphics Pipe-

line Interface, and the SDRAM Interface.

The GXm processor supports LVTTL (low voltage TTL)

technology. LVTTL technology allows the SDRAM inter-

face of the memory controller to run at frequencies up to

100 MHz.

The SDRAM clock is a function of the core clock. The

SDRAM bus can be run at speeds that range between 66

MHz and 100 MHz. The core clock can be divided down

from two to five in half clock increments to generate the

SDRAM clock. SDRAM frequencies between 79 MHz and

100 MHz are only supported for certain types of closed

systems and strict design rules must be adhered to. For

further details, please contact your local National Semi-

conductor technical support representative.

A basic block diagram of the memory controller is shown

in Figure 4-3.

Figure 4-3. Memory Controller Block Diagram

Address

Processor/PCI

Display Controller

Graphics Pipeline

Processor/PCI Address

Processor I/F

Display Controller I/F

Graphics Pipeline I/F

Arbiter

SDRAM

RASA#,RASB#

CKEA#, CKEB#

WEA#/WEB#

Configuration

MA[12:0]

BA[1:0]

Display Controller Address

Graphics Pipeline Address

Processor/PCI Data

Display Controller Data

Graphics Pipeline Data

Processor/PCI

Display Controller

MD[63:0]

Read Buffer

(16 Bytes)

Sequence

Controller

Timing

Controller

Registers

Control/MUX

Write Buffer (16 Bytes)

Graphics Controller

Write Buffer (16 Bytes)

Control

DQM[7:0]

CASA#,CASB#

CS[3:0]#

REF

Clock Divider

2, 2.5, 3, 3.5, 4

SDCLK[3:0]

Core Clock (ph2)

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