GXM datasheet(104/244 Pages) NSC

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104

Revision 3.1

Integrated Functions (Continued)

4.3.1

Memory Array Configuration

The memory controller supports up to two 64-bit, 168-pin

unbuffered

SDRAM

modules

(DIMM).

Each

DIMM

receives a unique set of RAS, CAS, WE, and CKE lines.

Each DIMM can have one or two 64-bit DIMM banks.

Each DIMM bank is selected by a unique chip select (CS).

There are four chip select signals to choose between a

total of four DIMM banks. Each DIMM bank also receives

auniqueSDCLK. Each DIMM bank canhavetwo or four

component banks. Component bank selection is done

through the bank address (BA) lines.

For example, 16 Mb SDRAMS have two component

banks and 64 Mb SDRAMs have two or four component

banks. For single DIMM bank modules, the memory con-

troller can support two DIMMS with a maximum of eight

component banks. For dual DIMM bank modules, the

memory controller can support two DIMMs with a maxi-

mum of 16 component banks. Up to 16 banks can be

open at the same time.

Figure 4-4. Memory Array Configuration

MA[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RASA#

CASA#

WEA#

CS1#

CS0#

CKEA

SDCLK0

SDCLK1

RASB#

CASB#

WEB#

CS3#

CS2#

CKEB

SDCLK2

SDCLK3

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

CAS#

WE#

S0#, S2#

CKE0

CK0, CK2

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

CAS#

WE#

S1#, S3#

CKE1

CK1, CK3

Bank 0

Bank 1

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

CAS#

WE#

S0#, S2#

CKE0

CK0, CK2

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

CAS#

WE#

S1#, S3#

CKE1

CK1, CK3

Bank 0

Bank 1

DIMM 1

DIMM 0

Geode™ GXm

Processor

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