MT9072AB datasheet(171/275 Pages) ZARLINK

171 / 275 page

MT9072

Data Sheet

171

Zarlink Semiconductor Inc.

17.2.2.10

Receive National Bit Data Register(R/W) Address(YC0 to YC4) Summary

17.2.3

Master Control Registers (Y00 - Y09) Bit Functions

Tables 147 to 157 describe the bit functions of each of the Master Control Registers in the MT9072 in E1 Mode.

Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2

with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB)

A11-A8). In addition, a simultaneous write to all 8 framers is possible by setting the MSB address to Y=8 (1000).

A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET, RSTC

or RST). The (#) indicates that a (0) or (1) is possible.

Binary Address

(A10-A0)

Hex

Address

Data Bits

(Upper byte B15 - B8 unused, B7 - B0 are shown)

yyyy 1111 1000

YC0

Receive National

Bits RN0 (Sa4)

RN0F1, RN0F3, RN0F5, RN0F7, RN0F9, RN0F11, RN0F13,

RN0F15

yyyy 1111 1001

YC1

Receive National

Bits RN1 (Sa5)

RN1F1, RN1F3, RN1F5, RN1F7, RN1F9, RN1F11, RN1F13,

RN1F15

yyyy 1111 1010

YC2

Receive National

Bits RN2 (Sa6)

RN2F1, RN2F3, RN2F5, RN2F7, RN2F9, RN2F11, RN2F13,

RN2F15

yyyy 1111 1011

YC3

Receive National

Bits RN3 (Sa7)

RN3F1, RN3F3, RN3F5, RN3F7, RN3F9, RN3F11, RN3F13,

RN3F15

yyyy 1111 0100

YC4

Receive National

Bits RN4 (Sa8)

RN4F1, RN4F3, RN4F5, RN4F7, RN4F9, RN4F11, RN4F13,

RN4F15

yyyy 1011 0101-

yyyy 1011 1111

YC5-YC

not used

upper data byte (B15-8) is not used and may be any value if read

see the Register Group Address Summary for an explanation of yyyy and Y

Table 141 - Transmit National Bits Data Registers (R/W) Address (YFX) Summary (E1)

Bit Name

Functional Description

IMA

Inverse Mux for ATM Mode. Setting this bit high the I/O ports to allow for easy connection to one

of the Zarlink IMA devices such as the MT90220. DSTi becomes a serial 2.048 data stream. C4b

becomes a 4.096 MHz clock that clocks DSTi as the St-Bus. RXFPB becomes a framing pulse that

flags the E1 stream coming from the pin DSTo. The data from DSTo is clocked out on RXDLC. Set

this pin low for all other applications. Note that signalling operations CSTi/CSTo do not function

with the IMA Mode. The global control register 900 bit CK1 is ignored for this framer. 8.192 Mbit/s

backplane mode is not supported if IMA mode is selected on any one framer.

ASEL

(0)

AIS Select. This bit selects the criteria on which the detection of a valid alarm indication signal

(AIS=1 of register address Y11) is based. If zero, the criteria is fewer than three zeros in a two

frame period (512 bits). If one, the criteria is fewer than three zeros in each of two consecutive

double-frame periods (512 bits per double-frame).

Table 142 - Alarm and Framing Control Register Y00 (R/W Address Y00) (E1)

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