MT9072AB datasheet(173/275 Pages) ZARLINK

173 / 275 page

MT9072

Data Sheet

173

Zarlink Semiconductor Inc.

3AUTC

(0)

Automatic CRC-interworking. If zero, automatic CRC-interworking is activated. If one, it is

deactivated. See Framing Algorithm section, Table 13 for details.

2CRCM

(0)

CRC-4 Modification. If one, the transmit CRC-4 remainder is modified when the device is in

transmit transparent mode (TxTRS=1 of register address Y03) in accordance with the local

datalink. The received CRC-4 remainder from the originating node is modified to reflect only the

changes in the local transmit DataLink. If zero, time-slot 0 data from DSTi will not be modified in

transmit transparent mode. This feature can used for intermediate nodes where 2 end nodes are

commmunicating for framing/signalling and 2 intermediate nodes are sending datalink information

in accordance with appendix C of G.706.

1AUTY

(0)

Automatic Y-Bit Operation. This bit determines the source for the Remote Multiframe Alarm

Indication bit (the Y bit) of the transmit PCM30 signal (time-slot 16 bit 6 of every frame 0 of the CAS

multiframe). If zero, the source for the Y bit is the Y bit of the Receive Alignment Signals Status

alignment has been acquired (Y=0 of status register), and Y=1 when multiframe alignment has not

been acquired (Y=1 of status register).

If the AUTY bit is set to one, the Y bit is controlled through the Y bit of the CAS Control and Data

0MFRF

(0)

Multiframe Reframe. If one, for at least one frame, and then cleared, the selected framer (Y) will

initiate a search for a new signalling multiframe position. Reframing function is activated on the

one-to-zero transition of the MFRF bit.

The signalling multiframe algorithm will align to the first multiframe alignment signal pattern (MFAS

= 0000) it receives in the most significant nibble of channel 16 (status register address Y10 bit

MSYNC is zero). Signalling multiframing will be lost when two consecutive multiframes are

received in error.

Bit

Name

Functional Description

15-14

not used.

L32Z

(0)

Digital Loss of Signal Selection. If one, the threshold for digital loss of signal is 32

successive zeros. If zero, the threshold is set to 192 successive zeros.

ADSEQ

(0)

Digital Milliwatt or Digital Test Sequence. If one, the A-law digital milliwatt analog test

sequence will be selected by the Per Timeslot Control bits TTSTn and RTSTn (register

address Y90 to YAF). If zero, the PRBS 215-1 bit error rate test sequence will be selected by

the Per Timeslot Control bits TTSTn and RTSTn. The PRBS generator is reset whenever this

bit is set to 1.

DLBK

(0)

Digital Loopback. If one, all timeslots of DSTi are connected to DSTo on the PCM30 side of

the selected framer (Y). If zero, this feature is disabled. See Loopbacks section.

RLBK

(0)

Remote Loopback. If one, all timeslots received on RPOS/RNEG are connected to

TPOS/TNEG on the PCM30 side of the selected framer (Y). If zero, this feature is disabled.

See Loopbacks section.

9SLBK

(0)

ST-BUS Loopback. If one, all timeslots of DSTi are connected to DSTo on the ST-BUS side

of the selected framer (Y). If zero, this feature is disabled. See Loopbacks section.

Table 143 - Test, Error and Loopback Control Register (R/W Address Y01) (E1)

Bit Name

Functional Description

Table 142 - Alarm and Framing Control Register Y00 (R/W Address Y00) (E1)

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