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MT9072AB 데이터시트(PDF) 265 Page - Zarlink Semiconductor Inc

부품명 MT9072AB
상세설명  Octal T1/E1/J1 Framer
PDF  275 Pages
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제조업체  ZARLINK [Zarlink Semiconductor Inc]
홈페이지  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB 데이터시트(HTML) 265 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
265
Zarlink Semiconductor Inc.
Figure 66 - Transmit Data Link Pin Functional Timing
Bit
76543210
Example A - enable output
Example B - 12 kbit/s clock output
Sa4 to Sa8 clocked in by MT9072
Sa4, Sa7 and Sa8 clocked in by MT9072
Timeslot 0
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
Bit
7
Bit
6
Bit
5
Bit
4
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
Timeslot 31
Timeslot 1
Bit
Sa7
Bit
Sa8
Bit
Sa6
Bit
Sa4
Bit
Sa5
Bit
7
Bit
6
Bit
5
Bit
7
Bit
6
Bit
5
Bit
4
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
FPi
(ST-BUS F0i)
CKi
(ST-BUS C4i)
TxDLC - Note 3
(Output)
TxDL
(Input)
(2Mb/s)
TxDLC - Note 2
(Output)
ST-BUS
Bit Cells
2Mb/s
Internal
(ST-BUS C2)
ST-BUS
Bit Cells
8Mb/s
Bit
76543210
Bit
76543210
TS2
TS4
TS1
TS0
TS127
TS126
TS125
TS124
TS3
TS5
Bit
76543210
Bit
76543210
Bit
76543210
Bit
76543210
Bit
76543210
Bit
76543210
Bit
76543210
CKi
(ST-BUS C16i)
Example A - 20 kbit/s clock output
Sa4 to Sa8 clocked in by MT9072
TxDLC - Note 2
(Output)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Example B - enable output
Sa4, Sa7 and Sa8 clocked in by MT9072
TxDLC - Note 3
(Output)
FPi
(ST-BUS F16i)



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