LAN9250 datasheet(24/421 Pages) MICROCHIP

24 / 421 page

LAN9250

DS00001913A-page 24

 2015 Microchip Technology Inc.

TABLE 3-8:

MISCELLANEOUS PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

Power

Management

Event Output

PME

VO8/VOD8

When programmed accordingly this signal is

asserted upon detection of a wakeup event. The

polarity and buffer type of this signal is programma-

ble via the PME Enable (PME_EN) bit of the Power

Management Control Register (PMT_CTRL).

Refer to Section 6.0, "Clocks, Resets, and Power

Management," on page 37 for additional information

on the power management features.

Interrupt Output

IRQ

VO8/VOD8

Interrupt request output. The polarity, source and

buffer type of this signal is programmable via the

Interrupt Configuration Register (IRQ_CFG). For

more information, refer to Section 8.0, "System

Interrupts," on page 62.

System Reset

Input

RST#

VIS

(PU)

As an input, this active low signal allows external

hardware to reset the device. The device also con-

tains an internal power-on reset circuit. Thus this

signal may be left unconnected if an external hard-

ware reset is not needed. When used this signal

must adhere to the reset timing requirements as

detailed in the Section 19.0, "Operational Character-

istics," on page 399.

Regulator

Enable

REG_EN

When tied to 3.3 V, the internal 1.2 V regulators are

enabled.

Test Mode

TESTMODE

VIS

(PD)

This pin must be tied to VSS for proper operation.

Crystal Input

OSCI

ICLK

External 25 MHz crystal input. This signal can also

be driven by a single-ended clock oscillator. When

this method is used, OSCO should be left uncon-

nected.

Crystal Output

OSCO

OCLK

External 25 MHz crystal output.

Crystal +1.2 V

Power Supply

OSCVDD12

Supplied by the on-chip regulator unless configured

for regulator off mode via REG_EN.

Crystal Ground

OSCVSS

Crystal ground.

Reserved

RESERVED

This pin is reserved and must be left unconnected

for proper operation.

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