LAN9250 datasheet(64/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 64

 2015 Microchip Technology Inc.

• Link Up (Link Status Asserted)

• Auto-Negotiation LP Acknowledge

• Parallel Detection Fault

• Auto-Negotiation Page Received

In order for an interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled

in the corresponding PHY Interrupt Mask Register (PHY_INTERRUPT_MASK), the PHY Interrupt Event Enable

(PHY_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via the

IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the Ethernet PHY interrupts, refer to Section 12.2.9, "PHY Interrupts," on page 220.

8.2.3

GPIO INTERRUPTS

Each GPIO of the device is provided with its own interrupt. The top-level GPIO Interrupt Event (GPIO) bit of the Interrupt

Status Register (INT_STS) provides indication that a GPIO interrupt event occurred in the General Purpose I/O Interrupt

Status and Enable Register (GPIO_INT_STS_EN). The General Purpose I/O Interrupt Status and Enable Register (GPI-

O_INT_STS_EN) provides enabling/disabling and status of each GPIO interrupt.

In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt must be enabled

in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), the GPIO Interrupt Event

Enable (GPIO_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ output must be enabled via

the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the GPIO interrupts, refer to Section 16.2.1, "GPIO Interrupts," on page 384.

8.2.4

HOST MAC INTERRUPTS

The top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN) provide the status and

enabling/disabling of multiple Host MAC related interrupts. All Host MAC interrupts are monitored and configured

directly within these two registers. The following Host MAC related interrupt events are supported:

• TX Stopped

• RX Stopped

• RX Dropped Frame Counter Halfway

•TX IOC

•RX DMA

• TX Status FIFO Overflow

• Receive Watchdog Time-Out

• Receiver Error

• Transmitter Error

• TX Data FIFO Overrun

• TX Data FIFO Available

• TX Status FIFO Full

• TX Status FIFO Level

• RX Dropped Frame

• RX Status FIFO Full

• RX Status FIFO Level

In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC interrupt event

must be enabled in the Interrupt Enable Register (INT_EN) and the IRQ output must be enabled via the IRQ Enable

(IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

Refer to the Interrupt Status Register (INT_STS) on page 69 and Section 11.0, "Host MAC," on page 139 for additional

information on bit definitions and Host MAC operation.

8.2.5

POWER MANAGEMENT INTERRUPTS

Multiple Power Management Event interrupt sources are provided by the device. The top-level Power Management

Interrupt Event (PME_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a Power Management

interrupt event occurred in the Power Management Control Register (PMT_CTRL).

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