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LAN9250 데이터시트(PDF) 57 Page - Microchip Technology |
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LAN9250 데이터시트(HTML) 57 Page - Microchip Technology |
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57 / 421 page ![]() 2015 Microchip Technology Inc. DS00001913A-page 57 LAN9250 speed_strap_1 PHY Speed Select Strap: This strap affects the default value of the following register bits: • Speed Select LSB (PHY_SPEED_SEL_LSB) bit of the PHY Basic Control Register (PHY_BASIC_CONTROL) • 10BASE-T Full Duplex and 10BASE-T Half Duplex bits of the PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) • PHY Mode (MODE[2:0]) bits of the PHY Special Modes Register (PHY_SPECIAL_MODES) Note: This has no effect when the PHY is in 100BASE-FX mode. Refer to the respective register definition sections for addi- tional information. 1b duplex_strap_1 PHY Duplex Select Strap: This strap affects the default value of the following register bits: • Duplex Mode (PHY_DUPLEX) bit of the PHY Basic Con- trol Register (PHY_BASIC_CONTROL) • 10BASE-T Full Duplex bit of the PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) • PHY Mode (MODE[2:0]) bits of the PHY Special Modes Register (PHY_SPECIAL_MODES) Refer to the respective register definition sections for addi- tional information. 1b FD_FC_strap_1 PHY Full-Duplex Flow Control Enable Strap: This strap affects the default value of the following register bits: • Asymmetric Pause bit of the PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) Note: This has no effect when the PHY is in 100BASE-FX mode. Refer to the respective register definition sections for addi- tional information. 1b manual_FC_strap_1 PHY Manual Flow Control Enable Strap: This strap affects the default value of the following register bits: • Asymmetric Pause and Symmetric Pause bit of the PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) Note: This has no effect when the PHY is in 100BASE-FX mode. Refer to the respective register definition sections for addi- tional information. 0b TABLE 7-1: SOFT-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED) Strap Name Description Pin / Default Value |
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