LAN9250 datasheet(247/421 Pages) MICROCHIP

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DS00001913A-page 247

LAN9250

12.2.18.12 PHYEDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG)

This register is used to Enable EEE functionality and control NLP pulse generation and the Auto-MDIX Crossover Time

of the PHY.

Index (decimal): 16

Size:

16 bits

Bits

Description

Type

Default

EDPD TX NLP Enable

Enables the generation of a Normal Link Pulse (NLP) with a selectable inter-

val while in Energy Detect Power-Down. 0=disabled, 1=enabled.

The Energy Detect Power-Down (EDPWRDOWN) bit in the PHY Mode Con-

trol/Status Register (PHY_MODE_CONTROL_STATUS) needs to be set in

order to enter Energy Detect Power-Down mode and the PHY needs to be in

the Energy Detect Power-Down state in order for this bit to generate the NLP.

Bit 3 of this register also needs to be set when setting this bit.

R/W

NASR

Note 10

14:13

EDPD TX NLP Interval Timer Select

Specifies how often a NLP is transmitted while in the Energy Detect Power-

Down state.

00b: 1 s

01b: 768 ms

10b: 512 ms

11b: 256 ms

R/W

NASR

Note 10

00b

EDPD RX Single NLP Wake Enable

When set, the PHY will wake upon the reception of a single Normal Link

Pulse. When clear, the PHY requires two link pluses, within the interval spec-

ified below, in order to wake up.

Single NLP Wake Mode is recommended when connecting to “Green” net-

work devices.

R/W

NASR

Note 10

11:10

EDPD RX NLP Max Interval Detect Select

These bits specify the maximum time between two consecutive Normal Link

Pulses in order for them to be considered a valid wake up signal.

00b: 64 ms

01b: 256 ms

10b: 512 ms

11b: 1 s

R/W

NASR

Note 10

00b

9:3

RESERVED

PHY Energy Efficient Ethernet Enable (PHYEEEEN)

When set, enables Energy Efficient Ethernet (EEE) operation in the PHY.

When cleared, EEE operation is disabled.

Refer to Section 12.2.11, "Energy Efficient Ethernet," on page 223 for addi-

tional information.

R/W

NASR

Note 10

Note 11

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