LAN9250 datasheet(300/421 Pages) MICROCHIP

300 / 421 page

LAN9250

DS00001913A-page 300

 2015 Microchip Technology Inc.

14.2

PTP Timestamp

This sub-module handles all PTP packet tasks related to recording timestamps of packets and inserting timestamps into

packets.

Modes supported are:

• Ordinary Clock, master and slave, one-step and two-step, end-to-end or peer-to-peer delay

- All 1588 packets are to and from the Host MAC

- RX and TX timestamps saved in registers for S/W

- RX timestamp stored in packet for ease of retrieval by S/W

- Egress timestamp of Sync packet inserted on-the-fly for one-step

- TX timestamp of Delay_Req packet stored in received Delay_Resp packet for ease of retrieval

- Correction Field and ingress timestamp of Pdelay_Req packet saved in registers for one-step turnaround time

- Correction Field of Pdelay_Resp packet automatically calculated and inserted on-the-fly for one-step

- PTP checksums and Ethernet FCS updated on-the-fly

- Ingress and egress timestamps corrected for latency

- Asymmetry corrections

- Peer delay correction on received Sync packets

Functions include:

• Detecting a PTP packet

- 802.3/SNAP or Ethernet II encoding

- Skipping over VLAN tags

- Ethernet, IPv4 or IPv6 message formats

- Skipping over IP extension headers

- Checking the MAC and / or the IP addresses

• Recording the timestamp of received packets into registers

- Accounting for the ingress latency

• Recording the timestamp of received packets into the packet and updating the layer 3 checksum and layer 2 FCS

fields

- Accounting for the ingress latency

• Forwarding or filtering PTP packets as needed to support ordinary clock mode

• Recording the timestamp of transmitted packets into registers

- Accounting for the egress latency

• One-step on-the-fly timestamp insertion for Sync packets and updating the layer 3 checksum and layer 2 FCS

• One-step on-the-fly turnaround time insertion for Pdelay_Req packets and updating the layer 3 checksum and

layer 2 FCS

Note:

Support for the IEEE 1588-2002 (v1) packet format is not provided.

14.2.1

RECEIVE FRAME PROCESSING

14.2.1.1

Ingress Time Snapshot

For each Ethernet frame, the receive frame processing detects the SFD field of the frame and temporarily saves the

current 1588 Clock value.

INGRESS LATENCY

The ingress latency is the amount of time between the start of the frame’s first symbol after the SFD on the network

medium and the point when the 1588 clock value is internally captured. It is specified by the RX Latency (RX_LA-

TENCY[15:0]) field in the 1588 Port Latency Register (1588_LATENCY) and is subtracted from the 1588 Clock value at

the detection of the SFD. The setting is used to adjust the internally captured 1588 clock value such that the resultant

timestamp more accurately corresponds to the start of the frame’s first symbol after the SFD on the network medium.

The ingress latency consists of the receive latency of the PHY and the latency of the 1588 frame detection circuitry. The

value depends on the port mode. Typical values are:

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