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LAN9250 데이터시트(PDF) 106 Page - Microchip Technology |
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LAN9250 데이터시트(HTML) 106 Page - Microchip Technology |
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106 / 421 page ![]() LAN9250 DS00001913A-page 106 2015 Microchip Technology Inc. 9.5.6.3 Internal Register Data Access The figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and 8-bit modes. This includes an index register write followed by either a data read or write. 16-BIT READ One of the Index Registers is set as described above. The address is then set to access the lower WORD of the corre- sponding Data Register and FIFOSEL is held low. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the Data Register. FIGURE 9-29: INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READ CS RD WR INDEX,1'b0 Index 15:8 D[15:8] A[4:1] INDEX,1'b1 8'hXX Index 7:0 D[7:0] 8'hXX FIFOSEL DATA,1'b0 Data 15:8 Data 7:0 DATA,1'b1 Data 31:24 Data 23:16 |
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