LAN9250 datasheet(113/421 Pages) MICROCHIP

113 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 113

LAN9250

8-BIT WRITE

FIFOSEL is set high and address bits 1 and 0 are set to access the lower BYTE of the FIFO, while address bits 4:2 are

don’t care. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats

for the remaining 3 BYTEs of the FIFO’s DWORD.

8-BIT BURST READ

FIFOSEL is set high and address bits 1 and 0 are set to access the lower BYTE of the FIFO, while address bits 4:2 start

at 0. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. Address bits 1 & 0 are then

cycled from 0 through 3 to access the next 3 BYTEs of the FIFO as RD is held active.

While RD is held active, address bits 4:2 are cycled from 0 through 7 to access the 8 DWORDs as address bits 1 & 0

are cycled from 0 through 3 to access each BYTE. Fresh data is supplied each time A[0] toggles. The FIFO is popped

when A[2] toggles.

FIGURE 9-39:

INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 8-BIT WRITE

FIGURE 9-40:

INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 8-BIT BURST READ

3'bXXX,2'b00

D[15:8]

A[4:0]

3'bXXX,2'b01

TX FIFO 7:0

D[7:0]

TX FIFO 15:8

FIFOSEL

3'bXXX,2'b10

3'bXXX,2'b11

TX FIFO 23:16

TX FIFO 31:24

Hi-Z

3'b000,2'b00

D[15:8]

A[4:0]

RX FIFO 7:0

D[7:0]

RX FIFO 15:8

FIFOSEL

RX FIFO 23:16 RX FIFO 31:24

Hi-Z

3'b000,2'b01

3'b000,2'b10

3'b000,2'b11

RX FIFO 7:0

RX FIFO 15:8 RX FIFO 23:16 RX FIFO 31:24

3'b111,2'b00

3'b111,2'b01

3'b111,2'b10

3'b111,2'b11

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