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LAN9250 데이터시트(PDF) 128 Page - Microchip Technology

부품명 LAN9250
상세설명  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 데이터시트(HTML) 128 Page - Microchip Technology

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LAN9250
DS00001913A-page 128
 2015 Microchip Technology Inc.
10.2.4.3
Dual Output Read
The SPI Dual Output Read instruction inputs the instruction code and the address and dummy bytes one bit per clock
and outputs the data two bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up
to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDOR instruction, 3Bh, is input into the SIO[0]
pin, followed by the two address bytes and 1 dummy byte. The address bytes specify a BYTE address within the device.
On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the
msbs of the LSB of the selected register. The remaining register di-bits are shifted out on subsequent falling clock edges.
The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time.
Figure 10-7 illustrates a typical single and multiple register dual output read.
FIGURE 10-7:
SPI DUAL OUTPUT READ
SPI Dual Output Read Single Register
SCK (active high)
SIO0
00
11
1
X
Instruction
1
Address
SIO1
d
e
c
Data
A
1
3
...
...
...
SPI Dual Output Read Multiple Registers
10
D
7
D
6
D
5
Z
Z
X
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
4
5
4
6
4
7
4
8
X
X
4
5
4
6
4
7
4
8
D
2
9
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SCK (active high)
SIO0 X
Instruction
Address
SIO1
d
e
c
A
1
3
...
...
Z
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
...
...
...
x
x
x
x
x
x
x
x
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
Dummy
x
x
x
x
x
x
x
x
Dummy
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
2
3
3
3
4
3
5
3
3
3
4
3
5
00
11
1
1
10
D
2
5
Data 1...
Data m
Data m+1... Data n
...
D
4
D
3
D
2
D
2
4
D
2
8
D
2
6
D
2
7
X
Data
D
7
D
6
D
5
D
4
D
3
D
2
D
2
9
D
2
5
D
2
4
D
2
8
D
2
6
D
2
7
D
7
D
6
D
5
D
4
D
3
D
2
Z
X
D
2
9
D
2
5
D
2
4
D
2
8
D
2
6
D
2
7
X
Data 1...
Data m
Data m+1... Data n



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