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ST72325AR7-Auto 데이터시트(PDF) 114 Page - STMicroelectronics

부품명 ST72325AR7-Auto
상세설명  SCI asynchronous serial interface
PDF  243 Pages
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ST72325AR7-Auto 데이터시트(HTML) 114 Page - STMicroelectronics

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Doc ID 13770 Rev 3
Figure 55.
Pulse width modulation mode timing example with 2 output compare
functions
Note:
On timers with only one Output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
13.3.7
Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality cannot be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1.
Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used.
2.
Load the OC1R register with the value corresponding to the period of the pulse if
OLVL1 = 0 and OLVL2 = 1 using the appropriate formula below according to the timer
clock source used.
3.
Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
4.
Select the following in the CR2 register:
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
–
Set the PWM bit.
–
Select the timer clock (CC[1:0]) (see Table 62: Timer clock selection).
COUNTER 34E2
34E2
FFFC
OLVL2
OLVL2
OLVL1
OCMP1
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
FFFC FFFD FFFE
2ED0
2ED1 2ED2



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