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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72325AR7-Auto 데이터시트(PDF) 210 Page - STMicroelectronics |
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ST72325AR7-Auto 데이터시트(HTML) 210 Page - STMicroelectronics |
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210 / 243 page  Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST72325xxx-Auto 210/243 Doc ID 13770 Rev 3 19.9 Control pin characteristics 19.9.1 Asynchronous RESET pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 130. Asynchronous RESET pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage(1) 0.3xVDD V VIH Input high level voltage(1) 0.7xVDD Vhys Schmitt trigger voltage hysteresis(2) 2.5 VOL Output low level voltage(3) VDD =5V, IIO = +2mA 0.2 0.5 IIO Input current on RESET pin 2 mA RON Weak pull-up equivalent resistor 20 30 120 k tw(RSTL)out Generated reset pulse duration Stretch applied on external pulse 0 42(4) µs Internal reset sources 20 30 42(4) th(RSTL)in External reset pulse hold time (5) 2.5 tg(RSTL)in Filtered glitch duration (6) 200 ns 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. Data guaranteed by design, not tested in production. 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments. |
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