| 전자부품 데이터시트 검색엔진 |
|
PDP83TG720SWCSTQ1 데이터시트(PDF) 46 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
PDP83TG720SWCSTQ1 데이터시트(HTML) 46 Page - Texas Instruments |
|
46 / 199 page ![]() 7.5 Programming 7.5.1 Strap Configuration The DP83TG720S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET_N pin or register access). The strap pins support 2-levels and 3-levels, which are described in greater detail below. Configuration of the device may be done through strapping or through serial management interface. Note Because strap pins are functional pins after reset is deasserted, they should not be connected directly to VCC or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation. R L R H VDDIO 6.3 kŸ ±25% Figure 7-18. 3 Level Strap Circuit R L R H VDDIO 9 NŸ ±25% Figure 7-19. 2 Level Strap Circuit Table 7-15. Recommended 3-level Strap Resistor Ratios MODE IDEAL RH (kΩ) for VDDIO = 3.3 V IDEAL RH (kΩ) for VDDIO = 2.5 V IDEAL RH (kΩ) for VDDIO = 1.8V 1 OPEN OPEN OPEN 2 13 8.5 4 3 4.5 2 0.8 DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |