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PDP83TG720SWCSTQ1 데이터시트(PDF) 89 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 89 Page - Texas Instruments |
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89 / 199 page ![]() 7.6.2.33 TDR_STATUS5 Register (Address = 0x30E) [reset = 0x0] TDR_STATUS5 is shown in Table 7-56. Return to the Summary Table. Table 7-56. TDR_STATUS5 Register Field Descriptions Bit Field Type Reset Description 15-5 RESERVED R 11b0000000 0000 Reserved 4 peak4_sign R 1b0 Peak 4 sign 3 peak3_sign R 1b0 Peak 3 sign 2 peak2_sign R 1b0 Peak 2 sign 1 peak1_sign R 1b0 Peak 1 sign 0 peak0_sign R 1b0 Peak 0 sign www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 89 |
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