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PDP83TG720SWCSTQ1 데이터시트(PDF) 15 Page - Texas Instruments

부품명 PDP83TG720SWCSTQ1
상세설명  DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY
PDF  199 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

PDP83TG720SWCSTQ1 데이터시트(HTML) 15 Page - Texas Instruments

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(1)
PARAMETER
TEST
CONDITIONS
MIN
NOM
MAX
UNIT
Tfall
Vod Fall Time
100
200
ps
Jitter
Output jitter
300
ps
25 MHz CRYSTAL REQUIREMENTS
Frequency
25
MHz
Frequency Tolerance and Stability Over temperature and aging
–100
100
ppm
Equivalent Series Resistance
50
Ω
OUTPUT CLOCK TIMING (CLKOUT)
Frequency
25
MHz
Duty Cycle ( With XI source as 50%)
48
52
%
Rise / Fall Time (10% - 90%)
2.5
ns
Jitter (RMS) (Slave Mode, MAC Iinterface : SGMII)
3.6
ps
Jitter (RMS) (Master Mode, MAC Iinterface : SGMII)
2.4
ps
Jitter (RMS) (Slave Mode, MAC Interface : RGMII)
11
ps
Jitter (RMS) (Master Mode, MAC Interface : RGMII)
15
ps
Sleep Entry and Wake-Up
MDI Energy Loss to Sleep Entry; INH Transition LOW
Normal Mode,
WAKE = LOW,
sleep_en = TRUE
4
ms
Local Wake-Up Pulse Duration
Sleep Mode, WAKE
pin
48
80
µs
MDI Energy Detection Wake-Up Pulse Duration
Sleep Mode
0.75
1.25
ms
(1)
Ensured by production test or characterization or design.
(2)
No supply sequencing constraint across power rails
(3)
In case OSC clock is delayed, additional reset is needed post Osc clock stablisation
(4)
Refer register[0x0430] for programmability of RX delay codes
(5)
PHY provides internal delays on TX_CLK to TX_D[3:0] to add additional skew upto 2 ns. Refer to register[0x0430] for programmability
www.ti.com
DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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