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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PDP83TG720SWCSTQ1 데이터시트(PDF) 97 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 97 Page - Texas Instruments |
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97 / 199 page  7.6.2.41 PHY_CTRL_1G Register (Address = 0x519) [reset = 0x3D] PHY_CTRL_1G is shown in Table 7-64. Return to the Summary Table. Table 7-64. PHY_CTRL_1G Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 1b0 Reserved 14 cfg_phy_ctrl_fallback_on_ energy_lost_loc_rcvr R/W 1b0 Allow phy control to go from TRAINING to COUNTDOWN to SILENT on energy lost and loc_rcvr lock Note : Should be enabled only if 0x519[13] is disabled 13 cfg_phy_ctrl_fallback_on_ energy_lost R/W 1b0 Allow phy control to go from TRAINING to COUNTDOWN to SILENT on energy lost Note : Should be enabled only if 0x519[14] is disabled 12 cfg_bypass_dsp_reset R/W 1b0 Bypass dsp reset from pcs 11 cfg_force_link_stat_val R/W 1b0 Forced link status value Valid only if 0x519[10] is set 10 cfg_force_link_stat R/W 1b0 Enable forcing link status value 9 cfg_link_control_override_ val R/W 1b0 Override Value for link control (only valid is autoneg is enabled) Valid only if 0x519[8] is set 8 cfg_link_control_override_ en R/W 1b0 Override Enable for link control (only valid is autoneg is enabled) 1b0 = Link_control override disbale 1b1 = Link_control override Eanable 7-0 cfg_minwait_timer_init R/W 8b00111101 Minwait timer value in us (value internally multiplied by 16) www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 97 |
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