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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PDP83TG720SWCSTQ1 데이터시트(PDF) 64 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 64 Page - Texas Instruments |
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64 / 199 page  7.6.2.8 MII_REG_12 Register (Address = 0x12) [reset = 0x0] MII_REG_12 is shown in Table 7-31. Return to the Summary Table. Table 7-31. MII_REG_12 Register Field Descriptions Bit Field Type Reset Description 15 link_qual_int R 1b0 Link quality bad interrupt status 14 energy_det_int R 1b0 Energy det change interrupt status 13 link_int R 1b0 Link status change interrupt status 12 RESERVED R 1b0 Reserved 11 esd_int R 1b0 ESD fault detected interrupt status 10 ms_train_done_int R 1b0 Training done interrupt status 9 RESERVED R 1b0 Reserved 8 RESERVED R 1b0 Reserved 7 link_qual_int_en R/W 1b0 Link quality bad interrupt enable 6 energy_det_int_en R/W 1b0 Energy det change interrupt enable 5 link_int_en R/W 1b0 Link status change interrupt enable 4 unused_int_3 R/W 1b0 Reserved 3 esd_int_en R/W 1b0 ESD fault detected interrupt enable 2 ms_train_done_int_en R/W 1b0 Training done interrupt enable 1 unused_int_2 R/W 1b0 Reserved 0 unused_int_1 R/W 1b0 Reserved DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 64 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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