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PDP83TG720SWCSTQ1 데이터시트(PDF) 83 Page - Texas Instruments

부품명 PDP83TG720SWCSTQ1
상세설명  DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY
PDF  199 Pages
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PDP83TG720SWCSTQ1 데이터시트(HTML) 83 Page - Texas Instruments

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7.6.2.27 TDR_CFG4 Register (Address = 0x305) [reset = 0x5]
TDR_CFG4 is shown in Table 7-50.
Return to the Summary Table.
Table 7-50. TDR_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-9
RESERVED
R
7b0000000
Reserved
8
mas_mode_tdr
R/W
1b0
Master slave config during TDR
7-6
pi_pud_ctrl_tdr
R/W
2b00
PUD control during TDR
5
pi_pud_clk_tdr
R/W
1b0
PUD clock during TDR
4-2
hpf_gain_tdr
R/W
3b001
HPF gain during TDR
1-0
pga_gain_tdr
R/W
2b01
PGA gain during TDR
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DP83TG720S-Q1
SNLS604 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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