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PDP83TG720SWCSTQ1 데이터시트(PDF) 87 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 87 Page - Texas Instruments |
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87 / 199 page ![]() 7.6.2.31 TDR_STATUS3 Register (Address = 0x30C) [reset = 0x0] TDR_STATUS3 is shown in Table 7-54. Return to the Summary Table. Table 7-54. TDR_STATUS3 Register Field Descriptions Bit Field Type Reset Description 15-8 peak2_amp R 8b00000000 Peak 2 amplitude in echo coeff 7-0 peak1_amp R 8b00000000 Peak 1 amplitude in echo coeff www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 87 |
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