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PDP83TG720SWCSTQ1 데이터시트(PDF) 76 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 76 Page - Texas Instruments |
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76 / 199 page ![]() 7.6.2.20 LPS_CFG3 Register (Address = 0x18C) [reset = 0x0] LPS_CFG3 is shown in Table 7-43. Return to the Summary Table. Table 7-43. LPS_CFG3 Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 8b00000000 Reserved 7 cfg_lps_pwr_mode_7 R/WMC,0 1b0 Reserved 6 cfg_lps_pwr_mode_6 R/WMC,0 1b0 Reserved 5 cfg_lps_pwr_mode_5 R/WMC,0 1b0 Reserved 4 cfg_lps_pwr_mode_4 R/WMC,0 1b0 Set to enter standby mode 3 cfg_lps_pwr_mode_3 R/WMC,0 1b0 Reserved 2 cfg_lps_pwr_mode_2 R/WMC,0 1b0 Reserved 1 cfg_lps_pwr_mode_1 R/WMC,0 1b0 Reserved 0 cfg_lps_pwr_mode_0 R/WMC,0 1b0 Set to enter normal mode DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 76 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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