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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PDP83TG720SWCSTQ1 데이터시트(PDF) 95 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 95 Page - Texas Instruments |
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95 / 199 page  7.6.2.39 LPS_CONTROL_2 Register (Address = 0x515) [reset = 0x808] LPS_CONTROL_2 is shown in Table 7-62. Return to the Summary Table. Table 7-62. LPS_CONTROL_2 Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 1b0 Reserved 14-8 cfg_wake_cg_cnt_th R/W 7b0001000 Number of continuous expected wake code groups required to acknowledge and set LPS wake command received. 7 RESERVED R 1b0 Reserved 6-0 cfg_sleep_cg_cnt_th R/W 7b0001000 Number of continuous expected sleep code groups required to acknowledge and set LPS sleep command received. www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 95 |
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