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PDP83TG720SWCSTQ1 데이터시트(PDF) 80 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 데이터시트(HTML) 80 Page - Texas Instruments |
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80 / 199 page ![]() 7.6.2.24 TDR_CFG1 Register (Address = 0x302) [reset = 0x45] TDR_CFG1 is shown in Table 7-47. Return to the Summary Table. Table 7-47. TDR_CFG1 Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 8b00000000 Reserved 7-4 cfg_forward_shadow R/W 4b0100 Forward shadow 3-2 cfg_post_silence_time R/W 2b01 Post silence time 2b00 = 0 ms 2b01 = 10 ms 2b10 = 100 ms 2b11 = 1000 ms 1-0 cfg_pre_silence_time R/W 2b01 Pre silence time 2b00 = 0 ms 2b01 = 10 ms 2b10 = 100 ms 2b11 = 1000 ms DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 80 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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