VR4102 datasheet(53/701 Pages) NEC

53 / 701 page

CHAPTER 1 INTRODUCTION

1.7 INSTRUCTION PIPELINE

The VR4102 has a 5-stage instruction pipeline.

Under normal circumstances, one instruction is issued each

cycle.

A detailed description of pipeline is provided in Chapter 4.

1.8 CLOCK INTERFACE

The VR4102 has the following nine clocks.

—

— CLKX1, CLKX2 (input)

These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core and

serial interface.

—

— RTCX1, RTCX2 (input)

These are oscillation inputs of 32.768 kHz, and used for PMU and RTC.

—

— FIRCLK (input)

This is a 48-MHz clock input, and used for FIR.

—

— PClock (internal)

This clock is used to control the pipeline used in the VR4100 CPU core, and for units relating to the pipeline.

This clock is generated from the clock input of CLKX1 and CLKX2 pins. Its frequency is determined by

CLKSEL[2..0] pins.

—

— MasterOut (internal)

This is a bus clock of the VR4100 CPU core, and used for interrupt control. Its frequency is 1/4 of PClock

frequency.

—

— TClock (internal)

This is an operation clock for VR4100 CPU core bus, internal bus of the VR4102, and on-chip peripheral unit.

In the current VR4102, its frequency is 1/2 of PClock frequency.

—

— BUSCLK (output)

This clock is supplied to the controller on the system bus. Its frequency in determined by CLKSEL[2..0] pins.

—

— HSPMCLK (output)

This clock is supplied to the external CODEC. Its frequency is determined by the HSPMCLKD register.

—

— HSPSCLK (input)

This is an operation clock for the external CODEC and the modem interface.

Figure 1-9 shows an external circuit of the clock oscillator.

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