VR4102 datasheet(93/701 Pages) NEC

93 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

Table 3-14. Jump Instruction

Instruction

Format and Description

Jump

J target

The contents of 26-bit target address is shifted left by two bits and combined with the high-order four

bits of the PC. The program jumps to this calculated address with a delay of one instruction.

Jump And Link

JAL target

The contents of 26-bit target address is shifted left by two bits and combined with the high-order four

bits of the PC. The program jumps to this calculated address with a delay of one instruction. The

address of the instruction following the delay slot is stored into r31 (link register).

Instruction

Format and Description

Jump Register

JR rs

The program jumps to the address specified in register rs with a delay of one instruction.

Jump And Link

JALR rs, rd

The program jumps to the address specified in register rs with a delay of one instruction.

The address of the instruction following the delay slot is stored into rd.

There are the following common restrictions for Tables 3-15 and 3-16.

(1) Branch address

All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to

the 16-bit offset (shifted left by 2 bits and sign-extended to 64 bits). All branches occur with a delay of one

instruction.

(2) Operation when unbranched

If the branch condition does not meet in executing a Likely instruction, the instruction in its delay slot is nullified.

For all other branch instructions, the instruction in its delay slot is unconditionally executed.

Remark The target instruction of the branch is fetched at the EX stage of the branch instruction. Comparison

of the operands of the branch instruction and calculation of the target address is performed at phase 2

of the RF stage and phase 1 of the EX stage of the instruction. Branch instructions require one cycle

of the branch delay slot defined by the architecture. Jump instructions also require one cycle of delay

slot. If the branch condition is not satisfied in a branch likely instruction, the instruction in its delay slot

is nullified.

funct

target

VR4102 데이터시트(PDF) 93 Page - NEC