VR4102 datasheet(82/701 Pages) NEC

82 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

3.2 INSTRUCTION CLASSES

3.2.1 Load and Store Instructions

Load and store are immediate (I-type) instructions that move data between memory and the general-purpose

registers. The only addressing mode that load and store instructions directly support is base register plus 16-bit

signed immediate offset.

(1) Scheduling a Load Delay Slot

A load instruction that does not allow its result to be used by the instruction immediately following is called a

delayed load instruction. The instruction slot immediately following this delayed load instruction is referred to as

the load delay slot.

In the VR4000 Series, a load instruction can be followed directly by an instruction that accesses a register that is

loaded by the load instruction. In this case, however, an interlock occurs for a necessary number of cycles. Any

instruction can follow a load instruction, but the load delay slot should be scheduled appropriately for both

performance and compatibility with the VR3000

TM Series microprocessors. For detail, see CHAPTER 4 VR4102

PIPELINE.

(2) Store Delay Slot

When a store instruction is writing data to a cache, the data cache is kept busy at the DC and WB stages. If an

instruction (such as load) that follows directly the store instruction accesses the data cache in the DC stage, a

hardware-driven interlock occurs. To overcome this problem, the store delay slot should be scheduled.

Table 3-1. Number of Delay Slot Cycles Necessary for Load and Store Instructions

Instruction

Necessary number of PCycles

Load

Store

(3) Defining Access Types

Access type indicates the size of a VR4102 processor data item to be loaded or stored, set by the load or store

instruction opcode. Access types and accessed byte are shown in Table 3-2

Regardless of access type or byte ordering (endianness), the address given specifies the low-order byte in the

addressed field. For a little-endian configuration, the low-order byte is the least-significant byte.

The access type, together with the three low-order bits of the address, define the bytes accessed within the

addressed doubleword (shown in Table 3-2). Only the combinations shown in Table 3-2 are permissible; other

combinations cause address error exceptions.

Tables 3-3 and 3-4 list the ISA-defined load/store instructions and expand-ISA instructions, respectively.

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