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VR4102 데이터시트(PDF) 96 Page - NEC

부품명 VR4102
상세설명  64/32-bit Microprocessor
PDF  701 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

VR4102 데이터시트(HTML) 96 Page - NEC

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CHAPTER 3 CPU INSTRUCTION SET SUMMARY
96
3.2.4 Special Instructions
Special instructions generate software exceptions.
Their formats are R-type (Syscall, Break). The Trap
instruction is available only for the VR4000 Series. All the other instructions are available for all VR Series.
Table 3-17. Special Instructions
Instruction
Format and Description
Synchronize
SYNC
Completes the load/store instruction executing in the current pipeline before the next load/store
instruction starts execution.
System Call
SYSCALL
Generates a system call exception, and then transits control to the exception handling program.
Breakpoint
BREAK
Generates a break point exception, and then transits control to the exception handling program.
Table 3-18. Special Instructions (Extended ISA) (1/2)
Instruction
Format and Description
Trap If Greater Than
Or Equal
TGE rs, rt
The contents of register rs are compared with that of register rt, treating both operands as signed
integers. If the contents of register rs are greater than or equal to that of register rt, an exception
occurs.
Trap If Greater Than
Or Equal Unsigned
TGEU rs, rt
The contents of register rs are compared with that of register rt, treating both operands as unsigned
integers. If the contents of register rs are greater than or equal to that of register rt, an exception
occurs.
Trap If Less Than
TLT rs, rt
The contents of register rs are compared with that of register rt, treating both operands as signed
integers. If the contents of register rs are less than that of register rt, an exception occurs.
Trap If Less Than
Unsigned
TLTU rs, rt
The contents of register rs are compared with that of register rt, treating both operands as unsigned
integers. If the contents of register rs are less than that of register rt, an exception occurs.
Trap If Equal
TEQ rs, rt
If the contents of registers rs and rt are equal, an exception occurs.
Trap If Not Equal
TNE rs, rt
If the contents of registers rs and rt are not equal, an exception occurs.
SPECIAL
rs
rt
funct
rd
sa
SPECIAL
rs
rt
funct
rd
sa



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