VR4102 datasheet(90/701 Pages) NEC

90 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

Table 3-10. Multiply/Divide Instructions

Instruction

Format and Description

Multiply

MULT rs, rt

The contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. The

64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be sign

extended.

Multiply Unsigned

MULTU rs, rt

The contents of registers rt and rs are multiplied, treating both operands as 32-bit unsigned integers.

The 64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be

sign extended.

Divide

DIV rs, rt

The contents of register rs are divided by that of register rt, treating both operands as 32-bit signed

integers. The 32-bit quotient is stored into special register LO, and the 32-bit remainder is stored into

special register HI. In the 64-bit mode, the operand must be sign extended.

Divide Unsigned

DIVU rs, rt

The contents of register rs are divided by that of register rt, treating both operands as 32-bit unsigned

integers. The 32-bit quotient is stored into special register LO, and the 32-bit remainder is stored into

special register HI. In the 64-bit mode, the operand must be sign extended.

Move From HI

MFHI rd

The contents of special register HI are loaded into register rd.

Move From LO

MFLO rd

The contents of special register LO are loaded into register rd.

Move To HI

MTHI rs

The contents of register rs are loaded into special register HI.

Move To LO

MTLO rs

The contents of register rs are loaded into special register LO.

Table 3-11. Multiply/Divide Instructions (Extended ISA) (1/2)

Instruction

Format and Description

Doubleword Multiply

DMULT rs, rt

The contents of registers rt and rs are multiplied, treating both operands as signed integers. The 128-

bit result is stored into special registers HI and LO.

Doubleword Multiply

Unsigned

DMULTU rs, rt

The contents of registers rt and rs are multiplied, treating both operands as unsigned integers. The

128-bit result is stored into special registers HI and LO.

Doubleword Divide

DDIV rs, rt

The contents of register rs are divided by that of register rt, treating both operands as signed integers.

The 64-bit quotient is stored into special register LO, and the 64-bit remainder is stored into special

Doubleword Divide

Unsigned

DDIVU rs, rt

The contents of register rs are divided by that of register rt, treating both operands as unsigned

integers. The 64-bit quotient is stored into special register LO, and the 64-bit remainder is stored into

special register HI.

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