VR4102 datasheet(12/701 Pages) NEC

12 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE ........................................................................................ 199

7.1

RESET FUNCTION................................................................................................................. 199

7.1.1 RTC Reset ................................................................................................................................... 199

7.1.2 RSTSW ........................................................................................................................................ 201

7.1.3 Deadman’s Switch...................................................................................................................... 202

7.1.4 Software Shutdown .................................................................................................................... 203

7.1.5 HALTimer Shutdown .................................................................................................................. 204

7.2

POWERON SEQUENCE ........................................................................................................ 205

7.3

RESET OF THE CPU CORE ............................................................................................... 207

7.3.1 Cold Reset................................................................................................................................... 207

7.3.2 Soft Reset.................................................................................................................................... 208

7.4

VR4102 PROCESSOR MODES ............................................................................................. 210

7.4.1 Power Modes .............................................................................................................................. 210

7.4.2 Privilege Mode ............................................................................................................................ 211

7.4.3 Reverse Endian .......................................................................................................................... 211

7.4.4 Bootstrap Exception Vector (BEV) ........................................................................................... 211

7.4.5 Cache Error Check ..................................................................................................................... 212

7.4.6 Parity Error Prohibit ................................................................................................................... 212

7.4.7 Interrupt Enable (IE) ................................................................................................................... 212

CHAPTER 8 CACHE MEMORY ........................................................................................................... 213

8.1

MEMORY ORGANIZATION ................................................................................................... 213

8.2

CACHE ORGANIZATION....................................................................................................... 214

8.2.1 Organization of the Instruction Cache (I-Cache) ..................................................................... 214

8.2.2 Organization of the Data Cache (D-Cache) .............................................................................. 215

8.2.3 Accessing the Caches ............................................................................................................... 216

8.3

CACHE OPERATIONS........................................................................................................... 217

8.3.1 Cache Write Policy ..................................................................................................................... 217

8.4

CACHE STATES .................................................................................................................... 218

8.5

CACHE STATE TRANSITION DIAGRAMS ......................................................................... 219

8.5.1 Data Cache State Transition...................................................................................................... 219

8.5.2 Instruction Cache State Transition ........................................................................................... 219

8.6

CACHE DATA INTEGRITY ................................................................................................... 220

8.7

MANIPULATION OF THE CACHES BY AN EXTERNAL AGENT .................................. 230

CHAPTER 9 CPU CORE INTERRUPTS ............................................................................................. 231

9.1

NON-MASKABLE INTERRUPT (NMI) .................................................................................. 231

9.2

ORDINARY INTERRUPTS ..................................................................................................... 231

9.3

SOFTWARE INTERRUPTS GENERATED IN CPU CORE ............................................... 232

9.4

TIMER INTERRUPT................................................................................................................ 232

9.5

ASSERTING INTERRUPTS ................................................................................................... 232

9.5.1 Detecting Hardware Interrupts .................................................................................................. 232

9.5.2 Masking Interrupt Signals.......................................................................................................... 234

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