VR4102 datasheet(7/701 Pages) NEC

7 / 701 page

PREFACE

Readers

This manual targets users who intends to understand the functions of the VR4102

and to design application systems using this microprocessor.

Purpose

This manual introduces the architecture and hardware functions of the VR4102 to

users, following the organization described below.

Organization

This manual consists of the following contents:

• Introduction

• Pipeline operation

• Cache organization and memory management system

• Exception processing

• Initialization interface

• Interrupts

• Peripheral units

• Instruction set details

How to read this manual

It is assumed that the reader of this manual has general knowledge in the fields of

electric engineering, logic circuits, and microcomputers.

The VR4000

TM in this manual includes the VR4400TM.

To learn in detail about the function of a specific instruction,

o Read Chapter 3 CPU Instruction Set Summary and Chapter 27 CPU

Instruction Set Details.

To learn about the overall functions of the VR4102,

o Read this manual in sequential order.

To learn about electrical specifications,

o Refer to Data Sheet which is separately available.

Legend

Data significance:

Higher on left and lower on right

Active low:

XXX# (trailing # after pin and signal names)

Numeric representation:

binary/decimal ... XXXX

hexadecimal ... 0xXXXX

Prefixes representing an exponent of 2 (for address space or memory capacity):

K (kilo)

10 = 1024

M (mega)

20 = 10242

G (giga)

30 = 10243

T (tera)

40 = 10244

P (peta)

50 = 10245

E (exa)

60 = 10246

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