VR4102 datasheet(84/701 Pages) NEC

84 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

Table 3-2. Load/store Instruction

Instruction

Format and Description

Load Byte

LB rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The bytes of the memory location specified by the address are sign extended and loaded into register rt.

Load Byte Unsigned

LBU rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The bytes of the memory location specified by the address are zero extended and loaded into register rt.

Load Halfword

LH rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The halfword of the memory location specified by the address is sign extended and loaded to register rt.

Load Halfword

Unsigned

LHU rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The halfword of the memory location specified by the address is zero extended and loaded to register rt.

Load Word

LW rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The word of the memory location specified by the address is sign extended and loaded to register rt. In the

64-bit mode, it is further sign extended to 64 bits.

Load Word Left

LWL rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

Shifts to the left the word whose address is specified so that the address-specified byte is at the left-

most position of the word. The result of the shift operation is merged with the contents of register rt

and loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits.

Load Word Right

LWR rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

Shifts to the right the word whose address is specified so that the address-specified byte is at the right-

most position of the word. The result of the shift operation is merged with the contents of register rt and

loaded to register rt. In the 64-bit mode, it is further sign extended to 64 bits.

Store Byte

SB rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The least significant byte of register rt is stored to the memory location specified by the address.

Store Halfword

SH rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The least significant halfword of register rt is stored to the memory location specified by the address.

Store Word

SW rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

The lower word of register rt is stored to the memory location specified by the address.

Store Word Left

SWL rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

Shifts to the right the contents of register rt so that the left-most byte of the word is in the position of the

address-specified byte. The result is stored to the lower word in memory.

Store Word Right

SWR rt, offset (base)

The offset is sign extended and then added to the contents of the register base to form the virtual address.

Shifts to the left the contents of register rt so that the right-most byte of the word is in the position of the

address-specified byte. The result is stored to the upper word in memory.

base

offset

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