HCS08 datasheet(156/316 Pages) NXP

156 / 316 page

Internal Clock Source (S08ICSV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

156

Freescale Semiconductor

•

CLKS bits are written to 00

•

IREFS bit is written to 1

•

RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to

39.0625 kHz.

In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by

the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency,

as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal

reference clock is enabled.

10.4.1.2

FLL Engaged External (FEE)

The FLL engaged external (FEE) mode is entered when all the following conditions occur:

•

CLKS bits are written to 00

•

IREFS bit is written to 0

•

RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz

In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by

the external reference clock.The FLL loop will lock the frequency to 1024 times the reference frequency,

as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external

reference clock is enabled.

10.4.1.3

FLL Bypassed Internal (FBI)

The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:

•

CLKS bits are written to 01

•

IREFS bit is written to 1.

•

BDM mode is active or LP bit is written to 0

In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL

clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 1024

times the reference frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC

communications, and the internal reference clock is enabled.

10.4.1.4

FLL Bypassed Internal Low Power (FBILP)

The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:

•

CLKS bits are written to 01

•

IREFS bit is written to 1.

•

BDM mode is not active and LP bit is written to 1

In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock

and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal

reference clock is enabled.

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