HCS08 datasheet(157/316 Pages) NXP

157 / 316 page

Internal Clock Source (S08ICSV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

157

10.4.1.5

FLL Bypassed External (FBE)

The FLL bypassed external (FBE) mode is entered when all the following conditions occur:

•

CLKS bits are written to 10.

•

IREFS bit is written to 0.

•

BDM mode is active or LP bit is written to 0.

In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL

clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 1024

times the reference frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for

BDC communications, and the external reference clock is enabled.

10.4.1.6

FLL Bypassed External Low Power (FBELP)

The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:

•

CLKS bits are written to 10.

•

IREFS bit is written to 0.

•

BDM mode is not active and LP bit is written to 1.

In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock

and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external

reference clock is enabled.

10.4.1.7

Stop

Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static

except in the following cases:

ICSIRCLK will be active in stop mode when all the following conditions occur:

•

IRCLKEN bit is written to 1

•

IREFSTEN bit is written to 1

ICSERCLK will be active in stop mode when all the following conditions occur:

•

ERCLKEN bit is written to 1

•

EREFSTEN bit is written to 1

10.4.2

Mode Switching

When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS

bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting

frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will

begin locking again after a few full cycles of the resulting divided reference frequency. The completion of

the switch is shown by the IREFST bit.

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