HCS08 datasheet(223/316 Pages) NXP

223 / 316 page

Serial Peripheral Interface (S08SPIV3)

MC9S08SG8 MCU Series Data Sheet, Rev.8

Freescale Semiconductor

223

Figure 15-3. SPI Module Block Diagram

15.1.3

SPI Baud Rate Generation

As shown in Figure 15-4, the clock source for the SPI baud rate generator is the bus clock. The three

prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate

select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256

to get the internal SPI master mode bit-rate clock.

SPI SHIFT REGISTER

SHIFT

CLOCK

SHIFT

DIRECTION

Rx BUFFER

FULL

Tx BUFFER

EMPTY

SHIFT

OUT

SHIFT

ENABLE

SPI SYSTEM

CLOCK

LOGIC

CLOCK GENERATOR

BUS RATE

CLOCK

MASTER/SLAVE

MODE SELECT

MODE FAULT

DETECTION

MASTER CLOCK

SLAVE CLOCK

SPI

INTERRUPT

REQUEST

PIN CONTROL

MASTER/

SLAVE

MOSI

(MOMI)

MISO

(SISO)

SPSCK

MODF

SPE

LSBFE

MSTR

SPRF

SPTEF

SPTIE

SPIE

MODFEN

SSOE

SPC0

BIDIROE

SPIBR

Tx BUFFER (WRITE SPID)

Rx BUFFER (READ SPID)

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