HCS08 datasheet(225/316 Pages) NXP

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Serial Peripheral Interface (S08SPIV3)

MC9S08SG8 MCU Series Data Sheet, Rev.8

Freescale Semiconductor

225

15.3

Modes of Operation

15.3.1

SPI in Stop Modes

The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction.

During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1

or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are

halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If

stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered.

15.4

The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for

transmit/receive data.

Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address

assignments for all SPI registers. This section refers to registers and control bits only by their names, and

a Freescale-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

15.4.1

SPI Control Register 1 (SPIC1)

This read/write register includes the SPI enable control, interrupt enables, and configuration options.

321

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Reset

000

100

Figure 15-5. SPI Control Register 1 (SPIC1)

Table 15-1. SPIC1 Field Descriptions

Field

Description

SPIE

SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)

and mode fault (MODF) events.

0 Interrupts from SPRF and MODF inhibited (use polling)

1 When SPRF or MODF is 1, request a hardware interrupt

SPE

SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes

internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.

0 SPI system inactive

1 SPI system enabled

SPTIE

SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).

0 Interrupts from SPTEF inhibited (use polling)

1 When SPTEF is 1, hardware interrupt requested

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