HCS08 datasheet(237/316 Pages) NXP

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Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

237

Table 16-2. TPMV2 and TPMV3 Porting Considerations

Action

TPMV3

TPMV2

Write to TPMxCnTH:L registers1

Any write to TPMxCNTH or TPMxCNTL registers

Clears the TPM counter

(TPMxCNTH:L) and the

prescaler counter.

Clears the TPM counter

(TPMxCNTH:L) only.

Read of TPMxCNTH:L registers1

In BDM mode, any read of TPMxCNTH:L registers

Returns the value of the TPM

counter that is frozen.

If only one byte of the

TPMxCNTH:L registers was

read before the BDM mode

became active, returns the

latched value of TPMxCNTH:L

from the read buffer (instead of

the frozen TPM counter value).

In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency

mechanism.

Does not clear this read

coherency mechanism.

Read of TPMxCnVH:L registers2

In BDM mode, any read of TPMxCnVH:L registers

Returns the value of the

TPMxCnVH:L register.

If only one byte of the

TPMxCnVH:L registers was

read before the BDM mode

became active, returns the

latched value of TPMxCNTH:L

from the read buffer (instead of

the value in the TPMxCnVH:L

registers).

In BDM mode, a write to TPMxCnSC

Clears this read coherency

mechanism.

Does not clear this read

coherency mechanism.

Write to TPMxCnVH:L registers

In Input Capture mode, writes to TPMxCnVH:L registers3

Not allowed.

Allowed.

In Output Compare mode, when (CLKSB:CLKSA not = 0:0),

writes to TPMxCnVH:L registers3

Update the TPMxCnVH:L

registers with the value of

their write buffer at the next

change of the TPM counter

(end of the prescaler

counting) after the second

byte is written.

Always update these registers

when their second byte is

written.

In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00),

writes to TPMxCnVH:L registers

Update the TPMxCnVH:L

registers with the value of

their write buffer after both

bytes were written and when

the TPM counter changes

from (TPMxMODH:L - 1) to

(TPMxMODH:L).

Note: If the TPM counter is a

free-running counter, then

this update is made when the

TPM counter changes from

0xFFFE to 0xFFFF.

Update after both bytes are

written and when the TPM

counter changes from

TPMxMODH:L to 0x0000.

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