HCS08 datasheet(261/316 Pages) NXP

261 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

261

Chapter 17



Development Support

17.1

Introduction

Development support systems in the HCS08 include the background debug controller (BDC) and the

on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that

provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The

BDC is also the primary debug interface for development and allows non-intrusive access to memory data

and traditional debug features such as CPU register modify, breakpoints, and single instruction trace

commands.

In the HCS08 Family, address and data bus signals are not available on external pins (not even in test

modes). Debug is done through commands fed into the target MCU via the single-wire background debug

interface. The debug module provides a means to selectively trigger and capture bus information so an

external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis

without having external access to the address and data signals.

17.1.1

Forcing Active Background

The method for forcing active background mode depends on the specific HCS08 derivative. For the

MC9S08SG8, you can force active background after a power-on reset by holding the BKGD pin low as

the device exits the reset condition. You can also force active background by driving BKGD low

immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.

Other causes of reset including an external pin reset or an internally generated error reset ignore the state

of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the

MCU will always reset into normal operating mode.

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