HCS08 datasheet(271/316 Pages) NXP

271 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

271

17.3

On-Chip Debug System (DBG)

Because HCS08 devices do not have external address and data buses, the most important functions of an

in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage

FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture

bus information and what information to capture. The system relies on the single-wire background debug

system to access debug control registers and to read results out of the eight stage FIFO.

The debug module includes control and status registers that are accessible in the user’s memory map.

These registers are located in the high register space to avoid using valuable direct page memory space.

Most of the debug module’s functions are used during development, and user programs rarely access any

of the control and status registers for the debug module. The one exception is that the debug system can

provide the means to implement a form of ROM patching. This topic is discussed in greater detail in

Section 17.3.6, “Hardware Breakpoints.”

17.3.1

Comparators A and B

Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking

circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry

optionally allows you to specify that a trigger will occur only if the opcode at the specified address is

actually executed as opposed to only being read from memory into the instruction queue. The comparators

are also capable of magnitude comparisons to support the inside range and outside range trigger modes.

Comparators are disabled temporarily during all BDC accesses.

The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the

CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data

bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an

additional purpose, in full address plus data comparisons they are used to decide which of these buses to

use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s

write data bus is used. Otherwise, the CPU’s read data bus is used.

The currently selected trigger mode determines what the debugger logic does when a comparator detects

a qualified match condition. A match can cause:

•

Generation of a breakpoint to the CPU

•

Storage of data bus values into the FIFO

•

Starting to store change-of-flow addresses into the FIFO (begin type trace)

•

Stopping the storage of change-of-flow addresses into the FIFO (end type trace)

17.3.2

Bus Capture Information and FIFO Operation

The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the

debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would

read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of

words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by

writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and

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