HCS08 datasheet(273/316 Pages) NXP

273 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

273

A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint

request. The usual action in response to a breakpoint is to go to active background mode rather than

continuing to the next instruction in the user application program.

The tag vs. force terminology is used in two contexts within the debug module. The first context refers to

breakpoint requests from the debug module to the CPU. The second refers to match signals from the

comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is

entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the

CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active

background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT

logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at

the compare address is actually executed. There is separate opcode tracking logic for each comparator so

more than one compare event can be tracked through the instruction queue at a time.

17.3.5

Trigger Modes

The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register

selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator

must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in

DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace),

or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected

(end trigger).

A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and

clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets

full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually

by writing a 0 to ARM or DBGEN in DBGC.

In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only

trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.

The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type

traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons

because opcode tags would only apply to opcode fetches that are always read cycles. It would also be

unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally

known at a particular address.

The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger.

Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the

corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with

optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines

whether the CPU request will be a tag request or a force request.

HCS08 데이터시트(PDF) 273 Page - NXP Semiconductors