HCS08 datasheet(305/316 Pages) NXP

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Appendix A Electrical Characteristics

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

305

A.12

AC Characteristics

This section describes ac timing characteristics for each peripheral system.

A.12.1

Control Timing

Table A-13. Control Timing

Num

Rating

Symbol

Min

Typ1

1 Typical values are based on characterization data at V

DD = 5.0V, 25C unless otherwise stated.

Max

Unit

Temp

Rated2

2 Electrical characteristics only apply to the temperature rated devices marked with x.

Sta

ndar

Gra

de 0

Bus frequency (tcyc = 1/fBus)

–40

C to 125 C

fBus

—

MHz

>125

C18

Internal low power oscillator period

–40

C to 125 C

tLPO

700

1500

s

>125

C

600

1500

External reset pulse width3

3 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to

override reset requests from internal sources.

textrst

100

—

Reset low drive4

4 When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t

cyc. After POR reset the bus clock

frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset to

0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.

trstdrv

66 x tcyc

—ns

Pin interrupt pulse width

Asynchronous path2

Synchronous path5

tILIH, tIHIL

100

1.5 x tcyc

——

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)5

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

5 Timing is shown with respect to 20% V

DD and 80% VDD levels. Temperature range –40C to 125C.

tRise, tFall

—

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)6

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

tRise, tFall

—

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