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P5021 데이터시트(PDF) 22 Page - NXP Semiconductors

부품명 P5021
상세설명  P5021 QorIQ Integrated Processor Data Sheet
PDF  155 Pages
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제조업체  NXP [NXP Semiconductors]
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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor
22
EMI2_MDIO
Management Data In/Out
AJ30
I/O
1.2 V
2, 18, 22
Ethernet Reference Clock
EC1_GTX_CLK125/
EC1_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
AK34
I
LVDD
27
EC2_GTX_CLK125/
EC2_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
AL33
I
LVDD
27
Ethernet External Timestamping
EC_XTRNL_TX_STMP1
External Timestamp Transmit 1
AM31
I
LVDD
—
EC_XTRNL_RX_STMP1
External Timestamp Receive 1
AK32
I
LVDD
—
EC_XTRNL_TX_STMP2/EC2_COL
External Timestamp Transmit 2
AJ31
I
LVDD
—
EC_XTRNL_RX_STMP2/EC2_CRS
External Timestamp Receive 2
AK31
I
LVDD
—
Three-Speed Ethernet controller 1
EC1_TXD3
Transmit Data
AP36
O
LVDD
35
EC1_TXD2
Transmit Data
AT34
O
LVDD
35
EC1_TXD1
Transmit Data
AR34
O
LVDD
35
EC1_TXD0
Transmit Data
AT35
O
LVDD
35
EC1_TX_EN
Transmit Enable
AR36
O
LVDD
15
EC1_GTX_CLK/
EC1_TX_ER
Transmit Clock Out (RGMII)
Transmit Error (MII)
AP35
O
LVDD
26
EC1_RXD3
Receive Data
AM33
I
LVDD
27
EC1_RXD2
Receive Data
AN34
I
LVDD
27
EC1_RXD1
Receive Data
AN35
I
LVDD
27
EC1_RXD0
Receive Data
AN36
I
LVDD
27
EC1_RX_DV
Receive Data Valid
AM34
I
LVDD
27
EC1_RX_CLK
Receive Clock
AM36
I
LVDD
27
EC1_RX_ER/TSEC_1588_TRIG_IN2
Receive Error (MII)
AK36
I
LVDD
—
EC1_COL/GPIO30/TSEC_1588_ALARM_OUT2
Collision Detect (MII)
AK35
O
LVDD
26
EC1_CRS/GPIO31/TSEC_1588_PULSE_OUT2
Carrier Sense (MII)
AJ34
O
LVDD
26
Three-Speed Ethernet controller 2
EC2_TXD3
Transmit Data
AT31
O
LVDD
35
EC2_TXD2
Transmit Data
AP30
O
LVDD
35
EC2_TXD1
Transmit Data
AR30
O
LVDD
35
EC2_TXD0
Transmit Data
AT30
O
LVDD
35
EC2_TX_EN
Transmit Enable
AR31
O
LVDD
15
Table 1. Pins listed by bus (continued)
Signal
Signal description
Package
pin number
Pin
type
Power
supply
Notes



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