P5021 datasheet(93/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.15.2

eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 26 and Figure 27.

Output low voltage

VOL

IOL = 100μA at

CVDD min

—0.125

× CV

V—

Output high voltage

VOH

IOH = –100 μA at

CVDD min

CVDD –0.2

—

Output low voltage

VOL

IOL = 2 mA at

CVDD min

—0.3

Notes:

1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.

2. Open drain mode for MMC cards only.

Table 51. eSDHC AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

SD_CLK clock frequency:

SD Full speed/high speed mode

MMC Full speed/high speed mode

fSHSCK

25/50

20/52

MHz

2, 4

SD_CLK clock low time—Full-speed/High-speed mode

tSHSCKL

10/7

—

SD_CLK clock high time—Full-speed/High-speed mode

tSHSCKH

10/7

—

SD_CLK clock rise and fall times

tSHSCKR/

tSHSCKF

—3

Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIVKH

—

3, 4, 5

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIXKH

2.5

—

4, 5

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

tSHSKHOV

–3

4, 5

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC

high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching

the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing

the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F

(fall).

2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD card and 0–20 MHz for an MMC card. In high-speed

mode, the clock frequency value can be 0–50 MHz for an SD card and 0–52 MHz for an MMC card.

3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not

exceed 1 ns. For any high speed or default speed mode SD card, the oneway routing delay between Host and Card on

SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.

4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST +CCARD ≤ 40 pF

5. The parameter values apply to both full speed and high speed modes.

Table 50. eSDHC interface DC electrical characteristics (continued)

For recommended operating conditions, see Table 3.

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

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