P5021 datasheet(92/155 Pages) NXP

92 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

This figure shows how the local bus AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.

Figure 25. GPCM Output timing diagram

2.15

Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

2.15.1

eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 50. eSDHC interface DC electrical characteristics

For recommended operating conditions, see Table 3.

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

Input high voltage

VIH

—0.625

× CV

—V

Input low voltage

VIL

—

0.25

× CV

Input/output leakage current

IIN/IOZ

—–50

μA—

Output high voltage

VOH

IOH = –100 μA at

CVDD min

0.75

× CV

—V

—

tarcs +tLBKLOV

LCLK

LAD[0:31]

LBCTL

tLBONOT

LCS_B

LGPL2/LOE_B

address

taddr

taoe +tLBKLOV

LWE_B

tawcs +tLBKLOV

tLBONOT

address

taddr

tawe +tLBKLOV

tLBKLOX

trc

toen

read data

write data

twen

twc

write

read

LALE

1 t

addr is programmable and determined by LCRR[EADC] and ORx[EAD].

2 t

arcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the applicable chip reference manual.

P5021 데이터시트(PDF) 92 Page - NXP Semiconductors

P5021 데이터시트(HTML) 92 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL