P5021 datasheet(81/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This figure shows the RGMII AC timing and multiplexing diagrams.

Figure 18. RGMII AC timing and multiplexing diagrams

2.12.3

Ethernet management interface

This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces. EMI1 is the PHY management interface

controlled by the MDIO controller associated with Frame Manager 1 1GMAC-1. EMI2 is the XAUI PHY management interface

controlled by the MDIO controller associated with Frame Manager 1 10GMAC-0.

Fall time (20%–80%)

tRGTF

—

0.75

—

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.

Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. The tSKRGT_RX specification implies that PC board design requires clocks to be routed such that an additional trace delay of

greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay

inside their chip. If so, additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speeds transitioned

between.

5. The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.

Table 36. RGMII AC timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Typ

Max

Unit

Notes

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