P5021 datasheet(62/155 Pages) NXP

62 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

This table shows the estimated power dissipation on the POVDD supply for the chip, at allowable voltage levels.

This table shows the estimated power dissipation on the VDD_LP supply for the chip, at allowable voltage levels.

2.5

Thermal

This table shows the thermal characteristics for the chip.

Table 8. POVDD power dissipation

Supply

Maximum

Unit

Notes

POVDD

450

Note:

1. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature

range per Table 3.

Table 9. VDD_LP Power Dissipation

Supply

Maximum

Unit

Note

VDD_LP (P5021 on, 105C)

1.5

VDD_LP (P5021 off, 70C)

195

VDD_LP (P5021 off, 40C)

132

Note:

1. VDD_LP = 1.0 V, TJ = 105°C.

2. When P5021 is off, VDD_LP may be supplied by battery power to the Zeroizable Master Key and other Trust Architecture

state. Board should implement a PMIC which switches VDD_LP to battery when P5021 is powered down. See P5040

Reference Manual Trust Architecture chapter for more information.

Table 10. Package thermal characteristics 6

Rating

Board

Symbol

Value

Unit

Notes

Junction to ambient, natural convection

Single-layer board (1s)

RΘJA

°C/W

1, 2

Junction to ambient, natural convection

Four-layer board (2s2p)

RΘJA

°C/W

1, 2

Junction to ambient (at 200 ft./min.)

Single-layer board (1s)

RΘJMA

°C/W

1, 2

Junction to ambient (at 200 ft./min.)

Four-layer board (2s2p)

RΘJMA

°C/W

1, 2

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