P5021 datasheet(134/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

134

3.1.6

Frequency options

This section discusses interface frequency options.

3.1.6.1

SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

3.1.6.2

Minimum platform frequency requirements for high-speed interfaces

The platform clock frequency must be considered for proper operation of high-speed interfaces as described below.

For proper PCI Express operation, the platform clock frequency must be greater than or equal to the values shown in these

figures.

Figure 49. Gen 1 PEX minimum platform frequency

Figure 50. Gen 2 PEX minimum platform frequency

Table 100. Synchronous DDR clock ratio

Binary Value of

MEM_PLL_RAT[10:14]

DDR:Platform CLK ratio

Set MEM_PLL_CFG=01

for platform CLK freq1

0_0001

1:1

>600 MHz

All Others

Reserved

—

Note:

1. Set RCW field MEM_PLL_CFG=0b01

Table 101. SYSCLK and platform frequency options

Platform:

SYSCLK

ratio

SYSCLK (MHz)

100

125

133.3

150

Platform frequency (MHz)1

1 Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy

removed)

5:1

625

666

750

6:1

600

750

800

7:1

700

8:1

800

527 MHz

PCI Express link width

()

--------------------------------------------------------------------------------

527 MHz

PCI Express link width

()

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